An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive, or insulative layers on a silicon wafer. A variety of fabrication processes require planarization of a layer on the substrate. For example, one fabrication step involves depositing a filler layer over a non-planar surface and planarizing the filler layer. For certain applications, the filler layer is planarized until the top surface of a patterned layer is exposed. For example, a metal layer can be deposited on a patterned insulative layer to fill the trenches and holes in the insulative layer. After planarization, the remaining portions of the metal in the trenches and holes of the patterned layer form vias, plugs, and lines to provide conductive paths between thin film circuits on the substrate.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier head. The exposed surface of the substrate is typically placed against a rotating polishing pad. The carrier head provides a controllable load on the substrate to push it against the polishing pad. Polishing slurry with abrasive particles is typically supplied to the surface of the polishing pad.
One problem in CMP is that variations in the slurry composition, the polishing pad condition, the relative speed between the polishing pad and the substrate, the initial thickness of the substrate layer, and the load on the substrate can cause variations in the material removal rate at different locations of the same substrate or the material remove rate of different substrates.